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ics9ems9633 idt tm /ics tm ultra mobile pc clock for embedded applications 1617?08/19/09 datasheet ultra mobile pc clock for embedded applications 1 recommended application: features/benefits: poulsbo based ultra-mobile pc (umpc) for embedded applications ? industrial temperature range compliant supports ulv cpus with 67 to 167 mhz cpu outputs dedicated test/sel and test/mode pins saves isolation resistors on pins cpu stop# input for power manangment fully integrated vreg integrated series resistors on differential outputs 1.5v vdd io operation, 3.3v vdd core and ref supply pin for ref -40 to +85c operating range ssop pin configuration output features: 3 - cpu low power differential push-pull pairs 3 - src low power differential push-pull pairs 1 - lcd100 sscd low power differential push-pull pair 1 - dot96 low power differential push-pull pair 1 - ref, 14.31818mhz, 3.3v se output ref 1 48 vddref_3.3 gndref 2 47 x1 vddcore_3.3 3 46 x2 fsc_l 4 45 clkpwrgd#/pd_3.3 test_mode 5 44 cpu_stop# test_sel 6 43 cput0_lpr sclk 7 42 cpuc0_lpr sdata 8 41 vddio_1.5 vddcore_3.3 9 40 gndcpu vddio_1.5 10 39 cput1_lpr dot96c_lpr 11 38 cpuc1_lpr dot96t_lpr 12 37 vddcore_3.3 gnddot 13 36 vddio_1.5 gndlcd 14 35 gndcpu lcd100c_lpr 15 34 cput2_lpr lcd100t_lpr 16 33 cpuc2_lpr vddio_1.5 17 32 fsb_l vddcore_3.3 18 31 *cr#2 *cr#0 19 30 srct2_lpr gndsrc 20 29 srcc2_lpr srcc0_lpr 21 28 gndsrc srct0_lpr 22 27 srct1_lpr *cr#1 23 26 srcc1_lpr vddcore_3.3 24 25 vddio_1.5 9ems9633 * indicates inputs with internal pull up of ~10kohm to 3.3v 48 ssop package
idt tm /ics tm ultra mobile pc clock for embedded applications 1617?08/19/09 ics9ems9633 ultra mobile pc clock for embedded applications 2 datasheet ssop pin description pin # pin name type description 1 ref out 14.318 mhz reference clock. 2 gndref pwr ground pin for the ref outputs. 3 vddcore_3.3 pwr 3.3v power for the pll core 4fsc_l in low threshold input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. 5test_mode in test_mode is a real time input to select between hi-z and ref/n divider mode while in test mode. refer to test clarification table. 6 test_sel in test_sel: latched input to select test mode 1 = all outputs are tri-stated for test 0 = all outputs behave normall y . 7 sclk in clock pin of smbus circuitry, 5v tolerant. 8 sdata i/o data pin for smbus circuitry, 3.3v tolerant. 9 vddcore_3.3 pwr 3.3v power for the pll core 10 vddio_1.5 pwr power suppl y for low power differential outputs, nominal 1.5v. 11 dot96c_lpr out complement clock of low power differential pair for 96.00mhz dot clock. no 50ohm resistor to gnd needed. no rs needed. 12 dot96t_lpr out true clock of low power differential pair for 96.00mhz dot clock. no 50ohm resistor to gnd needed. no rs needed. 13 gnddot pwr ground pin for dot clock output 14 gndlcd pwr ground pin for lcd clock output 15 lcd100c_lpr out complement clock of low power differential pair for lcd100 ss clock. no 50ohm resistor to gnd needed. no rs needed. 16 lcd100t_lpr out true clock of low power differential pair for lcd100 ss clock. no 50ohm resistor to gnd needed. no rs needed. 17 vddio_1.5 pwr power supply for low power differential outputs, nominal 1.5v. 18 vddcore_3.3 pwr 3.3v power for the pll core 19 *cr#0 in clock request for src0, 0 = enable, 1 = disable 20 gndsrc pwr ground pin for the src outputs 21 srcc0_lpr out complementary clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 22 srct0_lpr out true clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 23 *cr#1 in clock request for src1, 0 = enable, 1 = disable 24 vddcore_3.3 pwr 3.3v power for the pll core
idt tm /ics tm ultra mobile pc clock for embedded applications 1617?08/19/09 ics9ems9633 ultra mobile pc clock for embedded applications 3 datasheet ssop pin description (continued) pin # pin name type description 25 vddio_1.5 pwr power supply for low power differential outputs, nominal 1.5v. 26 srcc1_lpr out complementary clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 27 srct1_lpr out true clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 28 gndsrc pwr ground pin for the src outputs 29 srcc2_lpr out complementary clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 30 srct2_lpr out true clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 31 *cr#2 in clock request for src2, 0 = enable, 1 = disable 32 fsb_l in low threshold input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. 33 cpuc2_lpr out complementary clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 34 cput2_lpr out true clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 35 gndcpu pwr ground pin for the cpu outputs 36 vddio_1.5 pwr power supply for low power differential outputs, nominal 1.5v. 37 vddcore_3.3 pwr 3.3v power for the pll core 38 cpuc1_lpr out complementary clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 39 cput1_lpr out true clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 40 gndcpu pwr ground pin for the cpu outputs 41 vddio_1.5 pwr power suppl y for low power differential outputs, nominal 1.5v. 42 cpuc0_lpr out complementary clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 43 cput0_lpr out true clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 44 cpu_stop# in stops all cpu clocks, except those set to be free r unning clocks 45 clkpwrgd#/pd_3.3 in this 3.3v lvttl input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. this is an active low input. / asynchronous active high input pin used to place the device into a power down state. 46 x2 out crystal output, nominally 14.318mhz 47 x1 in crystal input, nominally 14.318mhz. 48 vddref_3.3 pwr power pin for the xtal and ref clo cks, nominal 3.3v
idt tm /ics tm ultra mobile pc clock for embedded applications 1617?08/19/09 ics9ems9633 ultra mobile pc clock for embedded applications 4 datasheet mlf pin configuration cput0_lpr cpuc0_lpr vddio_1.5 gndcpu cput1_lpr cpuc1_lpr vddcore_3.3 vddio_1.5 gndcpu cput2_lpr cpuc2_lpr fsb_l 48 47 46 45 44 43 42 41 40 39 38 37 cpu_stop# 1 36 *cr#2 clkpwrgd#/pd_3.3 235 srct2_lpr x2 334 srcc2_lpr x1 433 gndsrc vddref_3.3 532 srct1_lpr ref 631 srcc1_lpr gndref 730 vddio_1.5 vddcore_3.3 8 29 vddcore_3.3 fsc_l 928 *cr#1 te s t_mode 10 27 srct0_lpr test_sel 11 26 srcc0_lpr sclk_3.3 12 25 gndsrc 13 14 15 16 17 18 19 20 21 22 23 24 sdata_3.3 vddcore_3.3 vddio_1.5 dot96c_lpr dot96t_lpr gnddot gndlcd lcd100c_lpr lcd100t_lpr vddio_1.5 vddcore_3.3 *cr#0 * indicates inputs with internal pull up of ~10kohm to 3.3v 48-pin mlf, 6x6 mm, 0.4mm pitch ics9ems9633
idt tm /ics tm ultra mobile pc clock for embedded applications 1617?08/19/09 ics9ems9633 ultra mobile pc clock for embedded applications 5 datasheet mlf pin description pin # pin name type description 1 cpu_stop# in stops all cpu clocks, except those set to be free r unning clocks 2 clkpwrgd#/pd_3.3 in this 3.3v lvttl input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. this is an active low input. / asynchronous active high input pin used to place the device into a power down state. 3x2 outcr y stal output, nominall y 14.318mhz 4 x1 in crystal input, nominally 14.318mhz. 5 vddref_3.3 pwr power pin for the xtal and ref clo cks, nominal 3.3v 6 ref out 14.318 mhz reference clock. 7 gndref pwr ground pin for the ref outputs. 8 vddcore_3.3 pwr 3.3v power for the pll core 9fsc_l in low threshold input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. 10 test_mode in test_mode is a real time input to select between hi-z and ref/n divider mode while in test mode. refer to test clarification table. 11 test_sel in test_sel: latched input to select test mode 1 = all outputs are tri-stated for test 0 = all outputs behave normally. 12 sclk_3.3 in clock pin of smbus circuitr y , 3.3v tolerant. 13 sdata_3.3 i/o data pin for smbus circuitry, 3.3v tolerant. 14 vddcore_3.3 pwr 3.3v power for the pll core 15 vddio_1.5 pwr power suppl y for low power differential outputs, nominal 1.5v. 16 dot96c_lpr out complement clock of low power differential pair for 96.00mhz dot clock. no 50ohm resistor to gnd needed. no rs needed. 17 dot96t_lpr out true clock of low power differential pair for 96.00mhz dot clock. no 50ohm resistor to gnd needed. no rs needed. 18 gnddot pwr ground pin for dot clock output 19 gndlcd pwr ground pin for lcd clock output 20 lcd100c_lpr out complement clock of low power differential pair for lcd100 ss clock. no 50ohm resistor to gnd needed. no rs needed. 21 lcd100t_lpr out true clock of low power differential pair for lcd100 ss clock. no 50ohm resistor to gnd needed. no rs needed. 22 vddio_1.5 pwr power supply for low power differential outputs, nominal 1.5v. 23 vddcore_3.3 pwr 3.3v power for the pll core 24 *cr#0 in clock request for src0, 0 = enable, 1 = disable
idt tm /ics tm ultra mobile pc clock for embedded applications 1617?08/19/09 ics9ems9633 ultra mobile pc clock for embedded applications 6 datasheet mlf pin description (continued) pin # pin name type description 25 gndsrc pwr ground pin for the src outputs 26 srcc0_lpr out complementary clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 27 srct0_lpr out true clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 28 *cr#1 in clock request for src1, 0 = enable, 1 = disable 29 vddcore_3.3 pwr 3.3v power for the pll core 30 vddio_1.5 pwr power supply for low power differential outputs, nominal 1.5v. 31 srcc1_lpr out complementary clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 32 srct1_lpr out true clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 33 gndsrc pwr ground pin for the src outputs 34 srcc2_lpr out complementary clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 35 srct2_lpr out true clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 36 *cr#2 in clock request for src2, 0 = enable, 1 = disable 37 fsb_l in low threshold input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. 38 cpuc2_lpr out complementary clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 39 cput2_lpr out true clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 40 gndcpu pwr ground pin for the cpu outputs 41 vddio_1.5 pwr power supply for low power differential outputs, nominal 1.5v. 42 vddcore_3.3 pwr 3.3v power for the pll core 43 cpuc1_lpr out complementary clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 44 cput1_lpr out true clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 45 gndcpu pwr ground pin for the cpu outputs 46 vddio_1.5 pwr power supply for low power differential outputs, nominal 1.5v. 47 cpuc0_lpr out complementary clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 48 cput0_lpr out true clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed.
idt tm /ics tm ultra mobile pc clock for embedded applications 1617?08/19/09 ics9ems9633 ultra mobile pc clock for embedded applications 7 datasheet funtional block diagram power groups vdd gnd 41, 46 low power outputs 42 vddcore_3.3v 30 low power outputs 29 vddcore_3.3v 22 low power outputs 23 vddcore_3.3v 15 low power outputs 14 vddcore_3.3v 57 xtal, ref srcclk lcdclk dot 96mhz 18 pin number description 19 25, 33 cpuclk 40, 45 cpu(2:0) src(2:0) lcd ss-pll fslb ckpwrgd/pd# cpu_stop# cr#(2:0) testsel testmode control logic 96m non-ss pll lcd100_ssc cpu, src ss-pll ref osc x1 x2 dot96mhz fslc smbdat smbclk
idt tm /ics tm ultra mobile pc clock for embedded applications 1617?08/19/09 ics9ems9633 ultra mobile pc clock for embedded applications 8 datasheet absolute maximum ratings parameter symbol conditions min max units notes 3.3v supply voltage vddxxx_3.3 supply voltage 3.9 v 1,2 1.5v supply voltage vddxxx_1.5 supply voltage 3.9 v 1,2 3.3_input high voltage v ih3.3 3.3v inputs vdd_3.3+ 0.3v v1,2,3 minimum input voltage v il any input gnd - 0.5 v 1 storage temperature ts - -65 150 c1,2 human body model 2000 v 1,2 man machine model 200 v 1,2 notes: 1 guaranteed by design and characterization, not 100% tested in production. esd prot input esd protection 2 operation under these conditions is neither implied, nor guaranteed. 3 maximum input voltage is not to exceed maximum vdd electrical characteristics - input/supply/common output parameters parameter symbol conditions min max units notes ambient operating temp t ambientitemp no airflow -40 85 c 1 3.3v supply voltage vddxxx_3.3 3.3v +/- 5% 3.135 3.465 v 1 1.5v supply voltage vddxxx_1.5 1.5v - 5% to 3.3v + 5% 1.425 3.465 v 1 3.3v input high voltage v ihse3.3 single-ended inputs 2 v dd + 0.3 v 1 3.3v input low voltage v ilse3.3 single-ended inputs v ss - 0.3 0.8 v 1 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input leakage current i inres inputs with pull or pull down resistors. (cr# pins) v in = v dd , v in = gnd -200 200 ua 1 output high voltage v ohs e single-ended outputs, i oh = -1ma 2.4 v 1 output low voltage v olse single-ended outputs, i ol = 1 ma 0.4 v 1 low threshold input- high voltage v ih_fs 3.3 v +/-5% 0.7 1.5 v 1 low threshold input- low voltage v il_fs 3.3 v +/-5% v ss - 0.3 0.35 v 1 i dd_defaul t 3.3v supply, lcdpll off 65 ma 1 i dd_lcden 3.3v supply, lcdpll enabled 70 ma 1 i dd_io 1.5v supply, differential io current, all outputs enabled 55 ma 1 i dd_pd3.3 3.3v supply, power down mode 2 ma 1 i dd_pdio 1.5v io supply, power down mode 0.5 ma 1 input frequency f i v dd = 3.3 v 15 mhz 2 pin inductance l p in 7nh1 c in logic inputs 1.5 5 pf 1 c out output pin capacitance 6 pf 1 c inx x1 & x2 pins 5 pf 1 spread spectrum modulation frequency f ssmod triangular modulation 30 33 khz 1 operating supply current power down current input capacitance
idt tm /ics tm ultra mobile pc clock for embedded applications 1617?08/19/09 ics9ems9633 ultra mobile pc clock for embedded applications 9 datasheet ac electrical characteristics - input/common parameters parameter symbol conditions min max units notes clk stabilization t stab from vdd power-up or de- assertion of pd# to 1st clock 1.8 ms 1 tdrive_src t drsrc src output enable after cr# assertion 15 ns 1 tdrive_pd# t drpd differential output enable after pd# de-assertion 300 us 1 tdrive_cpu t drsrc cpu output enable after cpu_stop# de-assertion 10 ns 1 tfall_pd# t fa ll 5ns1 trise_pd# t rise 5ns1 fall/rise time of pd# and cpu_stop# inputs ac electrical characteristics - low power differential outputs parameter symbol conditions min max units notes rising edge slew rate t slr differential measurement 0.5 6 v/ns 1,2 falling edge slew rate t flr differential measurement 0.5 6 v/ns 1,2 rise/fall time variation t slvar single-ended measurement 125 ps 1 maximum output voltage v high includes overshoot 1150 mv 1 minimum output voltage v low includes undershoot -300 mv 1 differential voltage swing v swing differential measurement 300 mv 1 crossing point voltage v xabs single-ended measurement 300 550 mv 1,3,4 crossing point variation v xabsvar single-ended measurement 140 mv 1,3,5 duty cycle d cyc differential measurement 45 55 % 1 cpu jitter - cycle to cycle cpuj c2c differential measurement 85 ps 1 src jitter - cycle to cycle srcj c2c differential measurement 125 ps 1 dot jitter - cycle to cycle dotj c2c differential measurement 250 ps 1 cpu[2:0] skew cpu skew10 differential measurement 100 ps 1 src[2:0] skew src skew differential measurement 250 ps 1 electrical characteristics - ref-14.318mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 clock period t p eriod 14.318mhz output nominal 69.8203 69.8622 ns 2 absolute min/max period t abs 14.318mhz output nominal 69.8203 70.86224 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 output high current i oh v oh @min = 1.0 v, v oh @max = 3.135 v -33 -33 ma 1 output low current i ol v ol @min = 1.95 v, v ol @max = 0.4 v 30 38 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter t jcyc-cyc v t = 1.5 v 1000 ps 1
idt tm /ics tm ultra mobile pc clock for embedded applications 1617?08/19/09 ics9ems9633 ultra mobile pc clock for embedded applications 10 datasheet clock periods differential outputs with spread spectrum enabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock lg- -ssc -ppm error 0ppm + ppm error +ssc lg+ absolute period short-term average long-term average period long-term average short-term average period minimum absolute period minimum absolute period minimum absolute period nominal maximum maximum maximum src 100 9.87400 9.99900 9.99900 10.00000 10.00100 10.05130 10.17630 ns 1,2 cpu 100 9.91400 9.99900 9.99900 10.00000 10.00100 10.05130 10.13630 ns 1,2 cpu 133 7.41425 7.49925 7.49925 7.50000 7.50075 7.53845 7.62345 ns 1,2 cpu 166 5.91440 5.99940 5.99940 6.00000 6.00060 6.03076 6.11576 ns 1,2 clock periods differential outputs with spread spectrum disabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock lg- -ssc -ppm error 0ppm + ppm error +ssc lg+ absolute period short-term average long-term average period long-term average short-term average period minimum absolute period minimum absolute period minimum absolute period nominal maximum maximum maximum src 100 9.87400 9.99900 10.00000 10.00100 10.17630 ns 1,2 cpu 100 9.91400 9.99900 10.00000 10.00100 10.13630 ns 1,2 cpu 133 7.41425 7.49925 7.50000 7.50075 7.62345 ns 1,2 cpu 166 5.91440 5.99940 6.00000 6.00060 6.11576 ns 1,2 dot 96 10.16560 10.41560 10.41670 10.41770 10.66770 ns 1,2 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz signal name signal name notes symbol definition measurement window units measurement window units notes symbol definition electrical characteristics - smbus interface parameter symbol conditions min max units notes smbus voltage v dd 2.7 3.3 v 1 low-level output voltage v ol s m b @ i pullup 0.4 v 1 current sinking at v olsmb = 0.4 v i pullup smb data pin 4 ma 1 sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 maximum smbus operating frequency f smbus block mode 100 khz 1 notes on electrical characteristics: 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through vswing centered around differential zero 3 vxabs is defined as the voltage where clk = clk# 4 only applies to the differential rising edge (clk rising and clk# falling) 6 all long term accuracy and clock period specifications are guaranteed assuming that ref is at 14.31818mhz 7 operation under these conditions is neither implied, nor guaranteed. 5 defined as the total variation of all crossing voltages of clk rising and clk# falling. matching applies to rising edge rate of clk and falling edge of clk#. it is measured using a +/-75mv window centered on the average cross point where clk meets clk#.
idt tm /ics tm ultra mobile pc clock for embedded applications 1617?08/19/09 ics9ems9633 ultra mobile pc clock for embedded applications 11 datasheet table 1: cpu frequency select table fs l c 1 fs l b 1 cpu mhz src mhz dot mhz lcd mhz ref mhz 0 0 133.33 0 1 166.67 1 0 100.00 1 1 66.67 1. fs l c is a low-threshold input.please see v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. also refer to the test clarification table. 100.00 96.00 100.00 14.318 table 2: lcd spread select table (pin 20/21) b1b5 b1b4 b1b3 spread % comment 0 0 0 -0.5% lcd100 0 0 1 -1% lcd100 0 1 0 -2% lcd100 0 1 1 -2.5% lcd100 1 0 0 +/- 0.25 % lcd100 1 0 1 +/-0.5% lcd100 1 1 0 +/-1% lcd100 1 1 1 +/-1.25% lcd100 0 1 enable running running 1 x enable low/20k low 0 0 enable high low 0x disable low/20k low 0 0 enable running running running running 1 x x low/20k low low/20k low 0 1 enable low/20k low running running 0x disable low/20k low low/20k low ref power management table 0 enable running 1 xlow 0 disable low ref pd smbus register oe dot/lcd dot#/lcd# pd cr_x# smbus register oe src src# src, lcd, dot power management table cpu power management table pd cpu_stop# smbus register oe cpu cpu# table 3: cpu n-ste p pro g rammin g cpu ( mhz ) p default n ( hex ) 133.33 3 64 166.67 3 7d 100.00 4 64 200.00 2 64 = 4mhz x n/p = 4mhz x n/p fcpu = 4mhz x n/p = 4mhz x n/p
idt tm /ics tm ultra mobile pc clock for embedded applications 1617?08/19/09 ics9ems9633 ultra mobile pc clock for embedded applications 12 datasheet general smbus serial interface information for the ics9ems9633 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p byte n + x - 1 data byte count = x beginning byte n stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit ics (slave/receiver) controller (host) x byte ack ack data byte count = x ack slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack
idt tm /ics tm ultra mobile pc clock for embedded applications 1617?08/19/09 ics9ems9633 ultra mobile pc clock for embedded applications 13 datasheet byte 0 pll & divider enable register bit(s) pin # name description type 0 1 default 7 - pll1 enable this bit controls whether the pll driving the cpu and src clocks is enabled or not. rw 0 = disabled 1 = enabled 1 6 - pll2 enable this bit controls whether the pll driving the dot and clock is enabled or not. rw 0 = disabled 1 = enabled 1 5 - pll3 enable this bit controls whether the pll driving the lcd clock is enabled or not. rw 0 = disabled 1 = enabled 1 4- 0 3 - cpu divider enable this bit controls whether the cpu output divider is enabled or not. note: this bit should be automatically set to ?0? if bit 7 is set to ?0?. rw 0 = disabled 1 = enabled 1 2- src output divider enable this bit controls whether the src output divider is enabled or not. note: this bit should be automatically set to ?0? if bit 7 is set to ?0?. rw 0 = disabled 1 = enabled 1 1- lcd output divider enable this bit controls whether the lcd output divider is enabled or not. note: this bit should be automatically set to ?0? if bit 5 is set to ?0?. rw 0 = disabled 1 = enabled 1 0- dot output divider enable this bit controls whether the dot output divider is enabled or not. note: this bit should be automatically set to ?0? if bit 6 is set to ?0?. rw 0 = disabled 1 = enabled 1 byte 1 pll ss enable/control register bit(s) pin # name description type 0 1 default 7 pll1 ss enable this bit controls whether pll1 has spread enabled or not. spread spectrum for pll1 is set at -0.5% down-spread. note that pll1 drives the cpu and src clocks. rw 0 = disabled 1 = enabled 1 6 pll3 ss enable this bit controls whether pll3 has spread enabled or not. note that pll3 drives the ssc clock, and that the spread spectrum amount is set in bits 3-5. rw 0 = disabled 1 = enabled 1 5 0 4 0 3 0 2 0 1 0 0 0 reserved reserved reserved reserved see table 2: lcd spread select table pll3 fs select these 3 bits select the frequency of pll3 and the ssc clock when byte 1 bit 6 (pll3 spread spectrum enable) is set. rw
idt tm /ics tm ultra mobile pc clock for embedded applications 1617?08/19/09 ics9ems9633 ultra mobile pc clock for embedded applications 14 datasheet byte 2 output enable register bit(s) pin # name description type 0 1 default 7 cpu0 enable this bit controls whether the cpu[0] output buffer is enabled or not. rw 0 = disabled 1 = enabled 1 6 cpu1 enable this bit controls whether the cpu[1] output buffer is enabled or not. rw 0 = disabled 1 = enabled 1 5 cpu2 enable this bit controls whether the cpu[2] output buffer is enabled or not. rw 0 = disabled 1 = enabled 1 4 src0 enable this bit controls whether the src[0] output buffer is enabled or not. rw 0 = disabled 1 = enabled 1 3 src1 enable this bit controls whether the src[1] output buffer is enabled or not. rw 0 = disabled 1 = enabled 1 2 src2 enable this bit controls whether the src[2] output buffer is enabled or not. rw 0 = disabled 1 = enabled 1 1 dot enable this bit controls whether the dot output buffer is enabled or not. rw 0 = disabled 1 = enabled 1 0 lcd100 enable this bit controls whether the lcd output buffer is enabled or not. rw 0 = disabled 1 = enabled 1 byte 3 output control register bit(s) pin # name description type 0 1 default 7 0 6 0 5 ref enable this bit controls whether the ref output buffer is enabled or not. rw 0 = disabled 1 = enabled 1 4 3 2 cpu0 stop enable this bit controls whether the cpu[0] output buffer is free-running or stoppable. if it is set to stoppable the cpu[0] output buffer will be disabled with the assertion of cpu_stp#. rw free running stoppable 0 1 cpu1 stop enable this bit controls whether the cpu[1] output buffer is free-running or stoppable. if it is set to stoppable the cpu[1] output buffer will be disabled with the assertion of cpu_stp#. rw free running stoppable 0 0 cpu2 stop enable this bit controls whether the cpu[2] output buffer is free-running or stoppable. if it is set to stoppable the cpu[2] output buffer will be disabled with the assertion of cpu_stp#. rw free running stoppable 0 10 ref slew 00 = slow edge rate 01 = medium edge rate 10 = fast edge rate 11 = reserved rw these bits control the edge rate of the ref clock. reserved reserved
idt tm /ics tm ultra mobile pc clock for embedded applications 1617?08/19/09 ics9ems9633 ultra mobile pc clock for embedded applications 15 datasheet byte 4 c pu pll n register bit(s) pin # name control function type 0 1 default bit 7 1 bit 6 1 bit 5 1 bit 4 1 bit 3 1 bit 2 1 bit 1 1 bit 0 cpu n div8 n divider prog bit 8 rw 0 byte 5 c pu pll/n register bit(s) pin # name control function type 0 1 default bit 7 cpu n div7 rw x bit 6 cpu n div6 rw x bit 5 cpu n div5 rw x bit 4 cpu n div4 rw x bit 3 cpu n div3 rw x bit 2 cpu n div2 rw x bit 1 cpu n div1 rw x bit 0 cpu n div0 rw x byte 6 reserved bit(s) pin # name control function type 0 1 default bit 7 1 bit 6 1 bit 5 1 bit 4 1 bit 3 0 bit 2 0 bit 1 1 bit 0 1 byte 7 reserved bit(s) pin # name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved see table 3: cpu n-step programming default depends on latched input frequency. default for cpu = 166 is 7dh. default for all other frequencies is 64h. reserved reserved reserved reserved reserved
idt tm /ics tm ultra mobile pc clock for embedded applications 1617?08/19/09 ics9ems9633 ultra mobile pc clock for embedded applications 16 datasheet byte 8 reserved bit(s) pin # name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 byte 9 lcd100 pll n register bit(s) pin # name control function type 0 1 default bit 7 lcd100 n div7 r x bit 6 lcd100 n div6 r x bit 5 lcd100 n div5 r x bit 4 lcd100 n div4 r x bit 3 lcd100 n div3 r x bit 2 lcd100 n div2 r x bit 1 lcd100 n div1 r x bit 0 lcd100 n div0 r x byte 10 status readback register bit(s) pin # name description type 0 1 default 7 37 fsb frequency select b r latch 6 9 fsc frequency select c r latch 5 24 cr0# readbk real time cr0# state indicator r cr0# is low cr0# is high x 4 28 cr1# readbk real time cr1# state indicator r cr1# is low cr1# is high x 3 36 cr2# readbk real time cr2# state indicator r cr2# is low cr2# is high x 2 0 1 0 0 0 byte 11 revision id/vendor id register bit(s) pin # name description type 0 1 default 7 rev code bit 3 r x 6 rev code bit 2 r x 5 rev code bit 1 r x 4 rev code bit 0 r x 3 vendor id bit 3 r 0 2 vendor id bit 2 r 0 1 vendor id bit 1 r 0 0 vendor id bit 0 r 1 byte 12 device id register bit(s) pin # name description type 0 1 default 7 dev_id3 device id msb r 0 6 dev_id2 device id 2 r 0 5 dev_id1 device id 1 r 1 4 dev_id0 device id lsb r 1 3 0 2 0 1 0 0 0 reserved reserved reserved vendor id reserved reserved reserved reserved reserved reserved reserved reserved n divider programming byte9 bit(7:0) and byte8 bit7 see n-step programming formula reserved reserved reserved see table 1: cpu frequency select table reserved revision id (0 for a rev) vendor specific
idt tm /ics tm ultra mobile pc clock for embedded applications 1617?08/19/09 ics9ems9633 ultra mobile pc clock for embedded applications 17 datasheet byte 13 reserved register bit(s) pin # name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 byte 14 reserved register bit(s) pin # name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 byte 15 byte count register bit(s) pin # name control function type 0 1 default bit 7 0 bit 6 0 bit 5 bc5 byte count 5 rw 0 bit 4 bc4 byte count 4 rw 0 bit 3 bc3 byte count 3 rw 1 bit 2 bc2 byte count 2 rw 1 bit 1 bc1 byte count 1 rw 1 bit 0 bc0 byte count lsb rw 1 byte 41 n program enable register bit(s) pin # name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 cpu n enable enables cpu n programming rw disabled enabled 0 bit 0 lcd n enable enables lcd n programming rw disabled enabled 0 reserved reserved reserved reserved reserved bytes 16:40 are reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved specifies number of bytes to be read back during an smbus read. default is 0xf. reserved reserved reserved reserved reserved
idt tm /ics tm ultra mobile pc clock for embedded applications 1617?08/19/09 ics9ems9633 ultra mobile pc clock for embedded applications 18 datasheet test clarification table comments test_sel hw pin test_mode hw pin output <0.35v x normal >0.7v<0.35vhi-z >0.7v >0.7v ref/n h w power-up w/ test_sel = 1 to enter test mode cycle power to disable test mode test_mode -->low vth input test_mode is a real time input
idt tm /ics tm ultra mobile pc clock for embedded applications 1617?08/19/09 ics9ems9633 ultra mobile pc clock for embedded applications 19 datasheet mlf top mark information (9ems9633kilf) line 1. company name line 2. part number line 3. yyww = date code line 3. country of origin line 4. ####### = lot number 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 ics ems9633il yyww cofo ######
idt tm /ics tm ultra mobile pc clock for embedded applications 1617?08/19/09 ics9ems9633 ultra mobile pc clock for embedded applications 20 datasheet min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n a 0808 variations min max min max 48 15.75 16.00 .620 .630 10-0034 0.635 basic 0.025 basic common dimensions in millimeters in inches common dimensions reference doc.: jedec publication 95, mo-118 300 mil ssop n see variations see variations d mm. d (inch) symbol see variations see variations
idt tm /ics tm ultra mobile pc clock for embedded applications 1617?08/19/09 ics9ems9633 ultra mobile pc clock for embedded applications 21 datasheet dimensions a0.81.0 n 48 a1 0 0.05 n d 12 a3 n e 12 b 0.18 0.3 d x e basic 6.00 x 6.00 e d2 min. / max. 3.95 / 4.25 e2 min. / max. 3.95 / 4.25 l min. / max. 0.30 / 0.50 0.20 reference 0.40 basic 48l tolerance thermally enhanced, very thin, fine pitch quad flat / no lead plastic package dimensions symbol min. max. symbol top view index area d sawn singulation anvil singulation a 0. 08 c c a3 a1 seating plane e2 e2 2 l (n -1)x e (ref.) & n n even n e d2 2 d2 (re f.) & odd 1 2 e 2 (typ.) (ref.) (ref.) if n & n (n -1)x b thermal base n or chamfer 4x 0.6 x 0.6 max optional e d n n d d d are even ordering information part/order number shipping packaging package temperature 9ems9633bkilf tubes 48-pin mlf -40 to +85 c 9ems9633bkilft tape and reel 48-pin mlf -40 to +85 c 9EMS9633BFILF tubes 48-pin ssop -40 to +85 c 9EMS9633BFILFt tape and reel 48-pin ssop -40 to +85 c parts that are ordered with a ?lf? suffix to the part number are the pb-free configuration and are rohs compliant. due to package size constraints, actual top-side marking may differ from the full orderable part number.
ics9ems9633 ultra mobile pc clock for embedded applications datasheet 22 innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa tm revision history rev. issue date description page # 0.1 07/31/09 initial release - a 08/19/09 released to final

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